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Car display interface design analysis of key technologies
2011-11-25 by seoer1

IMSResearch survey, car audio with video capabilities will be determined by the number of hosts 8.5 million in 2006 to grow to 26.6 million units in 2015. In order to both provide information to the driver, without distraction, the display needs to be installed in a location away from the car audio console, and rear screen projected onto the windshield. This combination of image sources and panel video interfaces are increasingly shifted from higher quality analog video technology, the RGB (red, green and blue) digital video format, which has become a standard graphics LCD module to use interface. Front-end display applications, the cable length is usually maintained at 1-3 m range, while the rear seat entertainment (RSE) unit of the cable you need to reach 8 meters or more. This connection supports gigabit / second data transfer rate, far exceeding the traditional car network baud rate, and can point serializer / deserializer (SerDes) solution perfectly. And transmit a wide parallel video bus compared to the chip set significantly reduces the transmission line and connector pin number in order to achieve a superior system-level benefits.

In order to meet the stringent automotive display interface requirements, such as high data throughput, ultra-thin wiring, advanced signal conditioning, detectability and low EMI (electromagnetic interference) and so on. U.S. National Semiconductor (NS) has developed DS90UR905 / 6 and DS90UR907/8SerDes chipset, the product is able resolution from QVGA (400x240) extended to 24-bit color depth XGA (1024x768), embedded clock SerDes solution. Wide range of pixel clock frequency only car manufacturer in its entire model range using a digital video display interface program, you can cover from a small two-screen dashboard panel, center console of the LCD to the larger size of the RSE display applications.

The concept of video applications and SerDes

Target applications for SerDes components of flat panel display link interface, it can be a long serial cable to connect the monitor image host. Typical examples include: the central information display (CID), dashboard, headrest monitors or entertainment on the preparation of the roof for rear seat passengers down type display module, shown in Figure 1. These new chipsets are NS launched "FPD-LinkII" series in a group, they can be a video source 27-bit digital RGB color information and control signals into a time clock information embedded in a single serial data stream on the twisted pair transmission. Chipset I / O (input / output) layer uses high speed differential signal, that is, the "true" (positive) terminal to transmit the actual signal at the same time, "complementary" (negative) terminal of the corresponding transmission opposite polarity signals.
Figure 2 describes the system level, the concept of video transmission. In addition to color and timing bits, there is an optional I2C control interface, it can be replaced with options to achieve by conventional component pin configuration. Chipset support for 18bpp (bits per pixel) or 24bpp color depth. Color display with three sub-pixels (red, green, blue) to define a single pixel. Since each pixel has 18 bits (6 red, 6 green and 6 blue), we can 26.2 million colors. Most people s eyes can see more than 10 million kinds of colors, which also explains why the use 24bpp has become a trend: It offers more than 16 million colors, enabling richer user experience and smooth color gradients. Has a very wide range of pixel clock: frequency from 5MHz to 65MHz, which makes the serial link speed from 140Mbps to 1.82Gbps, covering all the mainstream automotive display resolution.
Parallel LVCMOS input and output signals can be flexibly aligned each type synchronous transmitter and receiver to restore the output clock (PCLK) rising or falling edge, this feature greatly simplifies the controller and the serial device to the image to the deserializer LCD module supplier timing controller interface. Around the clock in the transmitter parallel within a certain band, SerDes chipset in the "pre-sync" when the receiver s PLL requires no external reference clock (or quartz oscillator). Even in every possible mode of transmission of random data synchronization can be assured that this is called "random data lock" feature. This not only saves the cost of reference component systems, but also eliminates another potential source of electromagnetic interference. The performance also can have a "hot", that does not require any special sort or training mode case, the deserializer can be sent to the serial data flow execution asserted / deasserted operation.

Once the receiver PLL locks the frequency of the transmitter, you can display the LOCK output flag pin in this state, the receiver output to ensure data integrity. DS90UR907 / 8 chipset DS90UR905 / 6 of all chipset features, ears difference is that the input and output signals are no longer sent LVCMOS parallel bus, but in accordance with an open industry standard "FPD-Link". Many modern graphics controller, display timing controller, ASIC and FPGA support this, "a serial-based" technology, which uses three for 18bpp data channel, or 24bpp for the four data channels, each of all the way parallel clock channel. Send electrical signals to follow open ANSI/TIA/EIA-644A standard, which is also called "LVDS" (low voltage differential signaling). Replace the conventional use of the LVCMOS interface technology advantages: the use of differential signals to reduce electromagnetic interference, and reduce the number of components of the pin, shown in Figure 3.

FPD-LinkII payload

In each pixel clock cycle, 28 "sub-symbolic" in the differential I / O on the after-division multiplexing, into a serial data stream. Embedded payload contains 24 color bits, three timing signals (horizontal sync-HS, vertical synchronization and Data Enable-VS-DE) and the additional bits. Interconnect 28x pixel clock rate. At 65MHz, this rate is converted to 1.82Gbps. Serial data stream by the end of "CLK1" HIGH-bit and at the end of "CLK0" LOW-bit limit, which can be achieved in each frame between the smooth transition of high and low, so the PLL can refer to the serial device to synchronize its and extract the embedded clock information. Two additional bits ("DCA" and "DCB" bit) is located in the middle of each frame, they are included in the DCA and DCB-bit embedded transition timing signal. Payload bit in order to reduce electromagnetic interference and improved harmonic signal quality, after randomization, balance and scrambling processing, while the exchange coupling to establish the DC balance.

Because the longer the cable, transmitter and receiver modules are more likely to occur between the ground potential drift, AC-coupled interface to the program through the transmission line can be used to achieve the potential decoupling capacitor in series. Serial device in the DC-balance encoding device and the corresponding deserializer DC balance in the decoder can be implemented on a serial link between the uniform distribution of high and low, to prevent the ISI (inter-symbol interference) effect and capacitance caused by the static model of obstruction. Configuration at both ends through the capacitor, the program can also be damaged or the cable net-to-ground voltage or short circuit board to provide input / output short circuit protection. Randomization and irregular not only ensure good eye opening, while minimizing interconnect line of electromagnetic interference, in general, the coding efficiency is higher than 85%.

Enhance the ability of the signal conditioning

Signal conditioning technology, to promote long-distance high-speed connection to play a crucial role in the serial device side using a signal reduction characteristics, Figure 4 is a signal example of the restore operation. This conversion of a string of bit stream, followed 0,1,000 and 1, top of the graph shows the single-ended (SE) waveform output in the terminal at the true value and potential is measured relative to the ground. Bottom of the graph shows the difference (DIFF) signal, equivalent to the terminal within the receiver s differential input voltage swing. For the first conversion, sending the first signal is 0, the formation of a fully differential swing. The next conversion is a 1, is also full voltage swing. Then in C, D and E is a set time frame 0, where 0 is the first full voltage swing. D and E with the time slot after the second and third arrival 0, the amplitude will decrease, that is the signal "restore" the. Therefore, the electrostatic charge in the cable will be limited, otherwise it will increase over time. This makes the last one sent in time slot 1 and F form a fully differential swing. Signal reduction in the transmission line characteristics are usually low-frequency signals to balance the high internal energy. The overall effect is a clear signal eye opening, formed by 1 or 0 after a long sequence of bits is a single conversion. Restore the signal level is programmable to adjust for the specific cable media to the best level of compensation.

In addition, the signal reduction feature adjustable differential output voltage (Vod) has a good effect, that it can make the long cable a differential output voltage (Vod) doubled. Not significantly reduce the signal to restore the signal receiver input signal amplitude can be restored. Deserializer input has an integrated cable equalizer, all the signal waveform in the regeneration when the input signal in terms of this function is equivalent to a relatively high-pass filter, can be partly eliminated by the transmission medium due to the low-pass filter effect. Equalizer gain in 1.5dB to 12dB between programmability. Of course, all the signal processing features to enhance co-ordination can also be used for long cable transmission in error-free data recovery to establish adequate eye opening.

Spread Spectrum Clock

Deserializer can be configured via an integrated spread spectrum clock (SSC) generator has been enhanced. At the receiver output bus terminal, which will result in output clock frequency and spectrum data over time to tens of KHz low-key system, a slight change in the rate. Shown in Figure 5, the frequency changes can occur in the vicinity of the center frequency of the name of pixel clock ("center spread spectrum modulation"), or toward a lower frequency ("down spread-spectrum modulation"). Spectrum extended up to the percentage of ± 2%. Spread spectrum clock will peak energy scattered in a wider spectral range, thus greatly reducing the noise level of electromagnetic interference, rather than at the same time point, a constant frequency to convert all of the output, then the radiation concentrated in a narrow band noise , all output data and output clock synchronization, which makes the data and clock effectively extended. Especially DS90UR906 receiver output with low voltage (LV) CMOS interface options, can significantly reduce the electromagnetic radiation.

Enhance the diagnostic capabilities

Another feature is the built-in self test (BIST) functions. In this mode, the transmitter sends a pseudo-random code sequence (PRBS). Within the receiver have the same sequence, and the receiver compares the bit pattern. In order to validate the overall test time and needs a minimum bit error rate to find the best compromise between the user can control the duration of BIST. Effective in the face of a load error, PASS pin will switch to clock mode. PASS pin placed BERT (Bit Error Rate Test) of the final result. If the test fails, indicating the emergence of one or more load errors; If the test shows that the PRBS sequence of transmitting and receiving no errors. In the remote link, BIST without any data generator, data logging or measurement system. Auto manufacturers can use to test the system BIST mode and check the link operation. It can also be used as a test bed for system development phase, in the case of no video source to send data across the link, but only applied to the transmitter clock signal. Stage in the service or troubleshooting, system testing can be used to verify the link to work, as in the lock on the client host or display the range of issues. When the car finally started, the display interface can be a routine check and verify connectivity.

More enhancements

More enhancements include an integrated termination resistors, which reduces the complexity of the circuit board design, so that lower cost, board space even smaller. Deserializer input terminal to provide a common mode filter pin. Recommended common-mode pin to ground through the capacitor to ensure stability and to ensure common-mode voltage of the frequency filter. This will reduce the level of electromagnetic radiation to the outside world, and can increase the resistance to external noise sources. Usually by high-current injection (BCI) test on digital video link resistance to external interference study, the use of up to 300mA to the side of the inductor current modulation to the cable shield cast. I / O library through VDDIO power, 1.8V or 3.3V available. This flexibility can take advantage of the advantages of low-level interfaces, and provides compatibility with downstream devices.

In general, when operating at 1.8V voltage components, as well as reduce the level of electromagnetic interference. Case of power failure, the deserializer output voltage can be set to tri-state (high impedance) or low resistance. Pixel clock (PCLK) state can be set to tri-state or low resistance, to choose to stop the internal oscillator. In the latter case, regardless of whether the input signal, the clock output will always be there. When the interface is only a short distance from the light load with bus connection, the receiver drive strength (RDS) feature minimizes output bus current consumption, slow down the output edge of the conversion rate and ultimately reduce electromagnetic interference. Chipset supports -40 ℃ to +105 ℃ the wide temperature range, suitable for different working environment of a variety of automotive electronic systems. The chipset LLP package, the space is small, and adopted the RoHS certification and AEC-Q100Grade2 standard comprehensive automotive certification.


New DS90UR905 / 6 and DS90UR907/8FPD-LinkII chipset has many system advantages and enhanced features. Parallel video bus clock by an embedded serialization to a single group, which reduces system cost and eliminates the clock / data skew problem, reducing noise, and extended to long-haul cable link distance. Chipset support from QWVGA to 24-bit color depth for all ordinary car LCD XGA resolution. To facilitate system design, certification and approval, the designer will bring more attention to how to reduce the EMI characteristics. This can be achieved without sacrificing the reliability requirements of the case to minimize the cost of protection. BIST pattern is conducive to plant diagnostic testing and practical application of troubleshooting and diagnostic tests are also beneficial. As FPD-LinkII series of third-generation chipset, its components based on proven and reliable IP protocol, and with previous generations of chipset for backwards compatibility. FPD-LinkII chipset series for the automotive industry on behalf of the optimized and true plug and play solution, because it is used in combination with low-density line does not affect performance, and high bandwidth, low power consumption, low EMI, durable and achieve self-link synchronization.

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